One step in designing integrated circuits (ICs) is the creation of a gate-level description of the circuit, known as a “netlist”, that lists the nets and the gate pins that must be connected together. A netlist may be generic or technology-specific. A generic netlist is one that has not yet been correlated to a technology-specific library of cells. The technology-specific netlist, also known as a “mapped netlist”, is one that has been mapped to a particular technology-specific library of cells. The cell library to which a technology-specific netlist is mapped defines cells that are to be including in the physical IC chip.
Some IC design efforts commence with a semiconductor platform having selected standard blocks of cells. Custom metal layers are added to the chip to customize the chip for a given requirement. The netlist defining the chip is mapped to the library of standard cell blocks to select the blocks for the chip, and to define the metal layers that connect the cell pins. The RapidChip methodology, available from LSI Logic Corporation of Milpitas, Calif., is an example of this type of semiconductor platform and design concept. The RapidChip methodology permits users to design and implement ICs at considerable savings in both time and expense.
Cell libraries increase in size and complexity with increasing size and complexity of ICs. Programmable ICs, such as metal programmable chip architectures, often require large cell libraries, rendering them particularly difficult to design. Increasing library size leads to increasing chances of error in cell selection, thus adding to the complexity and cost of the IC. There is a need, therefore, for smaller, or even single-cell, libraries that would not adversely affect design performance of the IC, particularly to IC design efforts and production using standard blocks of cells and customized metal layers, such as employed in the RapidChip methodology.